1. Field of the Invention
The present invention relates to a drive circuit for a switching element.
2. Description of Related Art
As described in Japanese Patent No. 3339311, there is known the so-called active gate control technique where the charge/discharge rate of the gate (electric charge in the gate) of an IGBT (Insulated Gate Bipolar Transistor) used as a semiconductor switching element is changed during a period from when charge/discharge of the gate is started to when the charge/discharge of the gate is completed. In more detail, the gate of the switching element is connected with a pair of first charge/discharge paths having a low resistance and a second pair of charge/discharge paths having a high resistance. The switching element is provided with an auxiliary emitter terminal from which a small current proportional to the collector current of the switching element is outputted. The auxiliary emitter terminal and the emitter of the switching element are connected to each other through an inductance.
In this technique, the process of discharging the gate is performed such that the gate is discharged through the pair of the first charge/discharge paths having the low resistance, and thereafter, when it is detected that the current flowing through the inductance starts to decrease due to reduction of the collector current, the gate is discharged through the pair of the second charge/discharge paths having the high resistance. According to the above described technique, it is possible to reduce the switching loss while suppressing increase of the surge voltage occurring when the operating state of the switching element is changed from on to off or vice versa.
Incidentally, the level of the collector-emitter voltage (the voltage across the collector and emitter of the switching element) at the time when the operating state of the switching element is changed greatly affects the switching loss and the reliability of the switching element. The level of the collector-emitter voltage varies due to various factors including the collector current.
In the above described technique, the rate of discharging the gate is changed at the moment when the current flowing through the inductance starts to decrease without exception, although the level of the collector-emitter voltage varies due to various factors. Hence, the above described technique involves various problems.
For example, when the collector current is large, the surge voltage becomes considerably high because the timing to reduce the gate discharging rate is late for this large collector current. This may cause the collector-emitter voltage to increase, and cause the switching loss to increase. For another example, it may occur that the gate charging/discharging rate is changed by the active gate control although there is a sufficient margin between the collector-emitter voltage and its allowable upper limit due to transition of the operation state of the switching element. In this case, the switching loss may increase because of reduction of the switching speed.